1. Field of the Invention
The invention relates in general to integrated jitter generators for adding a controlled amount of jitter to a signal during a jitter test.
2. Description of Related Art
When a transmitting IC transmits a digital data signal to a receiving IC, the transmitter typically synchronizes state changes in the digital data signal to leading (or trailing) edges of a periodic clock signal so that the state changes within the data signal will occur at predictable times. To produce a data sequence represented by successive states of the digital signal, the receiver need only digitize the data signal with an appropriate sampling phase and frequency. In some communication systems, a transmitter sending a digital data signal to a receiver also sends a clock signal to the receiver for controlling the timing with which the receiver samples the data signal. In other communication systems the receiver may include a “clock recovery” system for generating the sampling clock signal locally, using a feedback control system to adjust the phase and frequency of the sampling clock signal based on an analysis of data the receiver acquires by sampling the data signal.
While a transmitter may synchronize edges in a data signal to edges of a clock signal, a data signal can often appear somewhat jittery to a receiver. In a “jittery” digital signal, timing of signal edges vary to some extent relative to the timing of clock signal edges the receiver uses to sample the digital signal. Noise in the signal path conveying the data signal to the receiver can introduce jitter into the data signal. In a system where the transmitter sends a sampling clock signal to the receiver, noise in the clock signal path can cause the receiver to perceive the data signal to be jittery relative to the clock signal. In a receiver employing a clock recovery system to generate a local sampling clock signal, feedback errors or noise in the clock recovery system can cause jitter in the sampling clock signal, thereby causing the data signal to appear jittery relative to the sampling clock signal.
A receiver can tolerate some amount of jitter in a digital signal, but when a digital signal is too jittery, the receiver will not be able to correctly determine each successive state of the digital signal from the samples it acquires. Test specifications for an IC therefore sometimes require that during a logic test, one or more of the IC's input data or clock signals exhibit a specified amount of jitter so that the test will show whether the IC can tolerate that amount of jitter. A conventional IC tester produces a test signal that changes state at controlled times, and therefore might be able to supply a test signal input to an IC exhibiting some specified jitter pattern, provided that the IC tester can control test signal edge timing with sufficient resolution. But for high frequency test signals, a typical IC tester may not have sufficient timing resolution to do that. Even when an IC tester can generate a test signal having a controlled amount of amount of jitter, the signal path between the tester and the IC may be subject to noise. Thus when the test signal arrives at the IC, it may not only exhibit the controlled amount of jitter introduced by the IC tester, it may also exhibit an additional uncontrolled amount jitter introduced by noise in the signal path between the tester and the IC. The additional uncontrolled jitter in the test signal can cause an IC to fail a jitter test it might otherwise have passed in the absence of the uncontrolled jitter.
One way to reduce the influence of signal path noise on a test signal is to use a built-in, self-test (BIST) circuit within the IC to generate the test signal, thereby keeping the signal path for the TEST signal short and less subject to noise. BIST circuits are also useful for testing embedded subcircuits within an IC that are not directly accessible through the IC's IO terminals. U.S. Pat. No. 5,835,501 issued Nov. 10, 1998 to Dalmia et al describes a built-in, self-test (BIST) circuit incorporated into an IC for performing a jitter test on a circuit within an IC.
FIG. 1 illustrates a BIST circuit 10 employing principles taught by Dalmia et al for generating a jittery test signal supplied as input to a receiver 14 within an IC 12. Receiver 14 normally receives its input signal DIN from one of the IC's IO pins 16 via a multiplexer 18 within BIST circuit 10. The receiver includes a clock recovery system for generating a sampling clock signal and periodically samples DIN in response to the sampling clock signal to produce an output signal DOUT supplied as input to the IC's core logic 20 via another multiplexer 22. During a test, multiplexer 18 delivers a jittery test signal (TEST) produced by a data generator 24 within BIST circuit 10 as the input DIN to receiver 14 and delivers the DOUT signal of receiver 14 to a data analysis circuit 26 within BIST circuit 10. A clock synthesizer circuit 28 supplies a jittery clock signal CLK to data generator 24 for controlling edge timing in the TEST signal, and since the CLK signal is jittery, the TEST signal is jittery. Data analysis circuit 26 looks for errors in DOUT, and following the test, forwards results data to external equipment reporting whether it detected any errors.
FIG. 2 illustrates the clock synthesizer 16 taught by Dalmia et al. Clock synthesizer 28 includes a phase detector 29, a low pass filter 30 and a voltage-controlled oscillator (VCO) 31 for phase locking the CLK signal to the reference clock signal REFCLK. A sine wave generator 32, linked to the input of VCO 31 through a capacitor 33, causes a periodic error in the phase relationship between the CLK and REFCLK signals, thereby producing a controlled jitter in the CLK signal. One drawback to this circuit is that since phase locked loops are inherently jittery, clock synthesizer 28 the CLK signal will exhibit some additional jitter not caused by sine wave generator 32. Also sine wave generator 32 can require a substantial amount of chip space, Dalmia et al teach that it may be preferable to implement sine wave generator 32 off-chip. However, the signal path from sine wave generator 32 to VCO 31 will be long and more susceptible to noise, and therefore prone to adding still more uncontrollable jitter to the CLK signal. Also, that signal path requires use of one of the IC's limited number of IO terminals. Another disadvantage of clock synthesizer 28 of FIG. 2 is that the sine wave jitter pattern that it produces is neither programmable nor calibratable.
U.S. Patent Application Publication No. 2003/0041294A1 published Feb. 27, 2003 on an application filed Apr. 29, 2002 by Moll et al describes a jitter test system as illustrated in FIG. 3. A signal generator 34 supplies a test signal passing through a multiplexer 34, a delay unit 36, and another multiplexer 38 to a device under test (DUT) 38. Delay unit 36 variably delays the test signal with a delay controlled by an analog control signal generated by a control unit 40 so that the test signal input to DUT 38 exhibits a defined jitter pattern. Moll teaches that the control signal could be a rectangular wave, a sine wave or a triangle wave, and that the frequency and amplitude of the jitter in the test signal will vary in the same manner as the amplitude of the control signal. A receiving unit 39 monitors a DUT output signal to determine whether DUT 38 correctly responds to the jittery test signal. Control unit 40 may selectively configure multiplexers 35 and 37 so that the test signal output of signal generator 34 bypasses delay unit 36 when the test signal input to DUT 38 is to be jitter free.
The jitter generator system taught by Moll et al is advantageous over that taught by Dalmia et al in that the frequency and amplitude of the jitter it produces in a test signal can be changed by changing the nature of the analog signal produced by control unit 40. However, the jitter testing system taught by Moll et al has some drawbacks. First, control unit must include some type of programmable signal generator capable of producing an analog control signal having an adjustable frequency, amplitude and shape, and such a programmable signal generator can be relatively expensive. Also, since the signal path between delay unit 36 and DUT 38 is long, noise can cause the test signal input to DUT 38 to exhibit more jitter than specified, thereby causing the DUT to fail a test that it might otherwise have passed had the test signal not been subjected to that noise. Finally, the Moll's system provides no means for calibrating the delay provided by delay unit 36 so that the delay unit produces an expected jitter pattern in the test signal in response to an analog control signal of a particular nature. While the delay of delay unit 36 varies with the magnitude of the analog control signal supplied by control unit 40, due to process variations in delay unit 36 or to variations in ambient temperature, the relationship between the magnitude of the control signal input to delay unit 36 and the delay provided by delay unit 36 can be unpredictable. Thus while a user may be able to program control unit 40 to supply a tightly controlled analog control signal to delay unit 36, the actual jitter pattern it produces in the test signal can vary substantially from the user's expectations.
What is needed is a circuit for performing a jitter test on a signal receiver or on any other type of circuit within an IC using a test signal having a programmable and calibratable amount of jitter.